<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">

<head>
    <meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8" />
    <meta http-equiv="X-UA-Compatible" content="IE=9" />
    <meta name="generator" content="AmbiqMicro" />
    <title>Apollo3 BLEIF</title>
    <link href="../resources/tabs.css" rel="stylesheet" type="text/css" />
    <link href="../resources/bootstrap.css" rel="stylesheet" type="text/css" />
    <script type="text/javascript" src="../resources/jquery.js"></script>
    <script type="text/javascript" src="../resources/dynsections.js"></script>
    <link href="search/search.css" rel="stylesheet" type="text/css" />
    <link href="../resources/customdoxygen.css" rel="stylesheet" type="text/css" />
</head>

<body>
    <div id="top">
        <!-- do not remove this div, it is closed by doxygen! -->
        <div id="titlearea">
            <table cellspacing="0" cellpadding="0">
                <tbody>
                    <tr style="height: 56px;">
                        <td id="projectlogo">
                            <img alt="Logo" src="../resources/am_logo.png" />
                        </td>
                        <td style="padding-left: 0.5em;">
                            <div id="projectname">Apollo3  Register Documentation &#160;<span id="projectnumber">${version}</span></div>
                        </td>
                    </tr>
                </tbody>
            </table>
        </div>
        <!-- end header part -->
        <div id="navrow1" class="tabs">
            <ul class="tablist">
                <li class="current"><a href="../index.html"><span>Main&#160;Page</span></a>
                </li>
        </div>
        </li>
        </ul>
    </div>
    </div>
    <!-- top -->
    <!-- window showing the filter options -->
    <div class="header">
        <div class="headertitle">
            <div class="title">BLEIF - BLE Interface</div>
        </div>
    </div>
    <!--header-->
    <body>
        <br>
        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 class="panel-title"> BLEIF Register Index</h3>
            </div>
            <div class="panel-body">
                <table>
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000000:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#FIFO" target="_self">FIFO - FIFO Access Port</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000100:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#FIFOPTR" target="_self">FIFOPTR - FIFO size and remaining slots open values</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000104:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#FIFOTHR" target="_self">FIFOTHR - FIFO Threshold Configuration</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000108:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#FIFOPOP" target="_self">FIFOPOP - FIFO POP register</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x0000010C:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#FIFOPUSH" target="_self">FIFOPUSH - FIFO PUSH register</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000110:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#FIFOCTRL" target="_self">FIFOCTRL - FIFO Control Register</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000114:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#FIFOLOC" target="_self">FIFOLOC - FIFO Pointers</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000200:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#CLKCFG" target="_self">CLKCFG - I/O Clock Configuration</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x0000020C:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#CMD" target="_self">CMD - Command and offset Register</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000210:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#CMDRPT" target="_self">CMDRPT - Command Repeat Register</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000214:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#OFFSETHI" target="_self">OFFSETHI - High order offset bytes</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000218:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#CMDSTAT" target="_self">CMDSTAT - Command status</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000220:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#INTEN" target="_self">INTEN - IO Master Interrupts: Enable</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000224:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#INTSTAT" target="_self">INTSTAT - IO Master Interrupts: Status</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000228:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#INTCLR" target="_self">INTCLR - IO Master Interrupts: Clear</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x0000022C:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#INTSET" target="_self">INTSET - IO Master Interrupts: Set</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000230:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#DMATRIGEN" target="_self">DMATRIGEN - DMA Trigger Enable Register</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000234:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#DMATRIGSTAT" target="_self">DMATRIGSTAT - DMA Trigger Status Register</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000238:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#DMACFG" target="_self">DMACFG - DMA Configuration Register</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x0000023C:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#DMATOTCOUNT" target="_self">DMATOTCOUNT - DMA Total Transfer Count</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000240:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#DMATARGADDR" target="_self">DMATARGADDR - DMA Target Address Register</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000244:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#DMASTAT" target="_self">DMASTAT - DMA Status Register</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000248:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#CQCFG" target="_self">CQCFG - Command Queue Configuration Register</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x0000024C:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#CQADDR" target="_self">CQADDR - CQ Target Read Address Register</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000250:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#CQSTAT" target="_self">CQSTAT - Command Queue Status Register</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000254:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#CQFLAGS" target="_self">CQFLAGS - Command Queue Flag Register</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000258:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#CQSETCLEAR" target="_self">CQSETCLEAR - Command Queue Flag Set/Clear Register</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x0000025C:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#CQPAUSEEN" target="_self">CQPAUSEEN - Command Queue Pause Enable Register</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000260:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#CQCURIDX" target="_self">CQCURIDX - IOM Command Queue current index value. Compared to the CQENDIDX reg contents to generate the IDXEQ Pause event for command queue</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000264:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#CQENDIDX" target="_self">CQENDIDX - IOM Command Queue current index value. Compared to the CQCURIDX reg contents to generate the IDXEQ Pause event for command queue</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000268:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#STATUS" target="_self">STATUS - IOM Module Status Register</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000300:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#MSPICFG" target="_self">MSPICFG - SPI module master configuration</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000304:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#BLECFG" target="_self">BLECFG - BLE Core Control</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000308:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#PWRCMD" target="_self">PWRCMD - BLE Power command interface</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x0000030C:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#BSTATUS" target="_self">BSTATUS - BLE Core status</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000410:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#BLEDBG" target="_self">BLEDBG - BLEIF Master Debug Register</a>
                        </td>
                    </tr>

                </table>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="FIFO" class="panel-title">FIFO - FIFO Access Port</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C000</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Provides direct random access to both input and output FIFOs. The state of the FIFO is not disturbed by reading these locations (i.e., no POP will occur). FIFO0 is accessible from addresses 0x0 - 0x1C, and is used for data output from the IOM to external devices. These FIFO locations can be read and written directly.
FIFO locations 0x20 - 0x3C provide read only access to the input FIFO. These FIFO locations cannot be directly written by the MCU, and are updated only by the internal hardware. Writes to the FIFO0 will take effect immediately. The currently FIFO pointers
in register FIFOLOC indicate the current offset into each FIFO0 for the read and write operations.
Access to the FIFOs can only be done in word increments; Byte access and writes are not supported.
For push and pop style access to FIFO0 can be done using the FIFOPOP and FIFOPUSH registers below.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">FIFO
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>FIFO</td>
                            <td>RW</td>
                            <td>FIFO direct access. Only locations 0 - 3F will return valid information.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="FIFOPTR" class="panel-title">FIFOPTR - FIFO size and remaining slots open values</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C100</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="8">FIFO1REM
                                <br>0x0</td>

                            <td align="center" colspan="8">FIFO1SIZ
                                <br>0x0</td>

                            <td align="center" colspan="8">FIFO0REM
                                <br>0x0</td>

                            <td align="center" colspan="8">FIFO0SIZ
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:24</td>
                            <td>FIFO1REM</td>
                            <td>RO</td>
                            <td>The number of remaining data bytes slots currently in FIFO 1 (written by interface, read by MCU)<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>23:16</td>
                            <td>FIFO1SIZ</td>
                            <td>RO</td>
                            <td>The number of valid data bytes currently in FIFO 1 (written by interface, read by MCU)<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>15:8</td>
                            <td>FIFO0REM</td>
                            <td>RO</td>
                            <td>The number of remaining data bytes slots currently in FIFO 0 (written by MCU, read by interface)<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>7:0</td>
                            <td>FIFO0SIZ</td>
                            <td>RO</td>
                            <td>The number of valid data bytes currently in the FIFO 0 (written by MCU, read by interface)<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="FIFOTHR" class="panel-title">FIFOTHR - FIFO Threshold Configuration</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C104</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled, and also used during DMA to set the transfer size as a result of DMATHR trigger.
The WTHR is used to indicate when there are more than WTHR bytes of open FIFO locations available in the outgoing FIFO (FIFO0). The intended use to invoke an interrupt or DMA transfer that will refill the FIFO with a byte count up to this value.
The RTHR is used to indicate when there are more than RTHR bytes in the incoming FIFO (FIFO1) and a data transfer of this size can be supported, either through direct POP of the FIFO, or through DMA.
The value of both RTHR and WTHR are also used to set the data transfer size of DMA operations if DMATHR trigger is enabled.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="18">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="6">FIFOWTHR
                                <br>0x0</td>

                            <td align="center" colspan="2">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="6">FIFORTHR
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:14</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>13:8</td>
                            <td>FIFOWTHR</td>
                            <td>RW</td>
                            <td>FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the write FIFO contains FIFOWTHR free bytes, as indicated by the FIFO0REM field. This is intended to signal when a transfer of FIFOWTHR bytes can be done from the host to the IOM write FIFO to support large IOM write operations.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>7:6</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>5:0</td>
                            <td>FIFORTHR</td>
                            <td>RW</td>
                            <td>FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the read FIFO contains FIFORTHR valid bytes of data, as indicated by the FIFO1SIZ field. This is intended to signal when a data transfer of FIFORTHR bytes can be done from the IOM module to the host via the read FIFO to support large IOM read operations.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="FIFOPOP" class="panel-title">FIFOPOP - FIFO POP register</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C108</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Will advance the internal read pointer of the incoming FIFO (FIFO1) when read, if POPWR is not active. If POPWR is active, a write to this register is needed to advance the internal FIFO pointer.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">FIFODOUT
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>FIFODOUT</td>
                            <td>RW</td>
                            <td>This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0), the FIFO read pointer will be advanced by one word as a result of the read.
If the POPWR bit is set (1), the FIFO read pointer will only be advanced after a write operation to this register. The write data is ignored for this register.
If less than a even word multiple is available, and the command is completed, the module will return the word containing these bytes and undetermined data in the unused fields of the word.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="FIFOPUSH" class="panel-title">FIFOPUSH - FIFO PUSH register</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C10C</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Will write new data into the outgoing FIFO and advance the internal write pointer.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">FIFODIN
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>FIFODIN</td>
                            <td>RW</td>
                            <td>This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes).<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="FIFOCTRL" class="panel-title">FIFOCTRL - FIFO Control Register</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C110</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register, and also controls to reset the internal pointers of the FIFOs.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="30">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">FIFORSTN
                                <br>0x1</td>

                            <td align="center" colspan="1">POPWR
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:2</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>FIFORSTN</td>
                            <td>RW</td>
                            <td>Active low manual reset of the FIFO. Write to 0 to reset FIFO, and then write to 1 to remove the reset.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>POPWR</td>
                            <td>RW</td>
                            <td>Selects the mode in which 'pop' events are done for the FIFO read operations. A value of '1' will prevent a pop event on a read operation, and will require a write to the FIFOPOP register to create a pop event.
A value of '0' in this register will allow a pop event to occur on the read of the FIFOPOP register, and may cause inadvertent FIFO pops when used in a debugging mode.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="FIFOLOC" class="panel-title">FIFOLOC - FIFO Pointers</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C114</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Provides a read only value of the current read and write pointers. This register is read only and can be used along with the FIFO direct access method to determine the next data to be used for input and output functions.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="20">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="4">FIFORPTR
                                <br>0x0</td>

                            <td align="center" colspan="4">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="4">FIFOWPTR
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:12</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>11:8</td>
                            <td>FIFORPTR</td>
                            <td>RW</td>
                            <td>Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1), which is used to store read data returned from external devices during a read operation.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>7:4</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>3:0</td>
                            <td>FIFOWPTR</td>
                            <td>RW</td>
                            <td>Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0), which is used during write operations to external devices.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="CLKCFG" class="panel-title">CLKCFG - I/O Clock Configuration</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C200</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Provides clock related controls used internal to the BLEIF module, and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control.
This register is also used to enable the clock, which must be done prior to performing any IO transactions.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="19">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">DIV3
                                <br>0x0</td>

                            <td align="center" colspan="1">CLK32KEN
                                <br>0x0</td>

                            <td align="center" colspan="3">FSEL
                                <br>0x0</td>

                            <td align="center" colspan="7">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">IOCLKEN
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:13</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>12</td>
                            <td>DIV3</td>
                            <td>RW</td>
                            <td>Enable of the divide by 3 of the source IOCLK.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>11</td>
                            <td>CLK32KEN</td>
                            <td>RW</td>
                            <td>Enable for the 32Khz clock to the BLE module<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>10:8</td>
                            <td>FSEL</td>
                            <td>RW</td>
                            <td>Select the input clock frequency.<br><br>
                                 MIN_PWR              = 0x0 - Selects the minimum power clock. This setting should be used whenever the IOM is not active.<br>
                             HFRC                 = 0x1 - Selects the HFRC as the input clock.<br>
                             HFRC_DIV2            = 0x2 - Selects the HFRC / 2 as the input clock.<br>
                             HFRC_DIV4            = 0x3 - Selects the HFRC / 4 as the input clock.<br>
                             HFRC_DIV8            = 0x4 - Selects the HFRC / 8 as the input clock.<br>
                             HFRC_DIV16           = 0x5 - Selects the HFRC / 16 as the input clock.<br>
                             HFRC_DIV32           = 0x6 - Selects the HFRC / 32 as the input clock.<br>
                             HFRC_DIV64           = 0x7 - Selects the HFRC / 64 as the input clock.</td>
                        </tr>

                        <tr>
                            <td>7:1</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>IOCLKEN</td>
                            <td>RW</td>
                            <td>Enable for the interface clock. Must be enabled prior to executing any IO operations.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="CMD" class="panel-title">CMD - Command and offset Register</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C20C</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Writes to this register will start an IO transaction, as well as set various parameters for the command itself. Reads will return the command value written to the CMD register.
To read the number of bytes that have yet to be transferred, refer to the CTSIZE field within the CMDSTAT register.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="8">OFFSETLO
                                <br>0x0</td>

                            <td align="center" colspan="2">RSRVD54
                                <br>0x0</td>

                            <td align="center" colspan="2">CMDSEL
                                <br>0x0</td>

                            <td align="center" colspan="12">TSIZE
                                <br>0x0</td>

                            <td align="center" colspan="1">CONT
                                <br>0x0</td>

                            <td align="center" colspan="2">OFFSETCNT
                                <br>0x0</td>

                            <td align="center" colspan="5">CMD
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:24</td>
                            <td>OFFSETLO</td>
                            <td>RW</td>
                            <td>This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command. Offset bytes are transferred starting from the highest byte first.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>23:22</td>
                            <td>RSRVD54</td>
                            <td>RO</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>21:20</td>
                            <td>CMDSEL</td>
                            <td>RW</td>
                            <td>Command Specific selection information<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>19:8</td>
                            <td>TSIZE</td>
                            <td>RW</td>
                            <td>Defines the transaction size in bytes. The offset transfer is not included in this size.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>7</td>
                            <td>CONT</td>
                            <td>RW</td>
                            <td>Continue to hold the bus after the current transaction if set to a 1 with a new command issued.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>6:5</td>
                            <td>OFFSETCNT</td>
                            <td>RW</td>
                            <td>Number of offset bytes to use for the command - 0, 1, 2, 3 are valid selections. The second (byte 1) and third byte (byte 2) are read from the OFFSETHI register, and the low order byte is pulled from this register in the OFFSETLO field.
Offset bytes are transmitted highest byte first. E.g., if OFFSETCNT == 3, OFFSETHI[15:8] will be transmitted first, then OFFSETHI[7:0] then OFFSETLO.
If OFFSETCNT == 2, OFFSETHI[7:0] will be transmitted, then OFFSETLO.
If OFFSETCNT == 1, only OFFSETLO will be transmitted.
Offset bytes are always transmitted MSB first, regardless of the value of the LSB control bit within the module configuration.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>4:0</td>
                            <td>CMD</td>
                            <td>RW</td>
                            <td>Command for submodule.<br><br>
                                 WRITE                = 0x1 - Write command using count of offset bytes specified in the OFFSETCNT field<br>
                             READ                 = 0x2 - Read command using count of offset bytes specified in the OFFSETCNT field</td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="CMDRPT" class="panel-title">CMDRPT - Command Repeat Register</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C210</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Will repeat the next command for CMDRPT number of times. If CMDRPT is set to 1, the next command will be done 2 times in series. A repeat count of up to 31 is possible. Each command will be done as a separate command, but the data will
be treated as packed, and aligned to byte boundaries. This differs when executing separate commands without the CMDRPT set, as the data for each transaction is word aligned and any unused byte locations will be filled with 0 for read operations, or
discarded for write operations. For repeated commands (CMDRPT is nonzero), the data is packed and no bytes will be filled or discarded until the final command is done.
The register value is decremented for each repeated command and at the end of the repeated command set, will be set to zero. If subsequent commands are to be repeated, this register must be written again.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="27">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="5">CMDRPT
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:5</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>4:0</td>
                            <td>CMDRPT</td>
                            <td>RW</td>
                            <td>Count of number of times to repeat the next command.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="OFFSETHI" class="panel-title">OFFSETHI - High order offset bytes</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C214</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Provides the high order bytes of 2 or 3 byte offset transactions of the current command. Usage of these bytes is dependent on the OFFSETCNT field in the CMD register. If the OFFSETCNT == 3, the data located at OFFSETHI[15:0] will first be transmitted,
followed by OFFSETHI[7:0], followed by OFFSETLO (in the CMD register) prior to sending or receiving any transaction data (if programed via TSIZE field in the CMD register).
The offset bytes are always transmitted MSB first for all modules.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="16">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="16">OFFSETHI
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:16</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>15:0</td>
                            <td>OFFSETHI</td>
                            <td>RW</td>
                            <td>Holds the high order bytes of the 2 or 3 byte offset phase of a transaction.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="CMDSTAT" class="panel-title">CMDSTAT - Command status</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C218</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Provides status on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM.
These are read only fields and writes to the registers are ignored.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="12">RSRVD0
                                <br>0x0</td>

                            <td align="center" colspan="12">CTSIZE
                                <br>0x0</td>

                            <td align="center" colspan="3">CMDSTAT
                                <br>0x0</td>

                            <td align="center" colspan="5">CCMD
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:20</td>
                            <td>RSRVD0</td>
                            <td>RO</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>19:8</td>
                            <td>CTSIZE</td>
                            <td>RO</td>
                            <td>The current number of bytes still to be transferred with this command. This field will count down to zero.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>7:5</td>
                            <td>CMDSTAT</td>
                            <td>RO</td>
                            <td>The current status of the command execution.<br><br>
                                 ERR                  = 0x1 - Error encountered with command<br>
                             ACTIVE               = 0x2 - Actively processing command<br>
                             IDLE                 = 0x4 - Idle state, no active command, no error<br>
                             WAIT                 = 0x6 - Command in progress, but waiting on data from host</td>
                        </tr>

                        <tr>
                            <td>4:0</td>
                            <td>CCMD</td>
                            <td>RO</td>
                            <td>current command that is being executed<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="INTEN" class="panel-title">INTEN - IO Master Interrupts: Enable</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C220</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Set bits in this register to allow this module to generate the corresponding interrupt.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="15">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">B2MSHUTDN
                                <br>0x0</td>

                            <td align="center" colspan="1">B2MACTIVE
                                <br>0x0</td>

                            <td align="center" colspan="1">B2MSLEEP
                                <br>0x0</td>

                            <td align="center" colspan="1">CQERR
                                <br>0x0</td>

                            <td align="center" colspan="1">CQUPD
                                <br>0x0</td>

                            <td align="center" colspan="1">CQPAUSED
                                <br>0x0</td>

                            <td align="center" colspan="1">DERR
                                <br>0x0</td>

                            <td align="center" colspan="1">DCMP
                                <br>0x0</td>

                            <td align="center" colspan="1">BLECSSTAT
                                <br>0x0</td>

                            <td align="center" colspan="1">BLECIRQ
                                <br>0x0</td>

                            <td align="center" colspan="1">ICMD
                                <br>0x0</td>

                            <td align="center" colspan="1">IACC
                                <br>0x0</td>

                            <td align="center" colspan="1">B2MST
                                <br>0x0</td>

                            <td align="center" colspan="1">FOVFL
                                <br>0x0</td>

                            <td align="center" colspan="1">FUNDFL
                                <br>0x0</td>

                            <td align="center" colspan="1">THR
                                <br>0x0</td>

                            <td align="center" colspan="1">CMDCMP
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:17</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>16</td>
                            <td>B2MSHUTDN</td>
                            <td>RW</td>
                            <td>Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state  Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is deasserted (1 -> 0)<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>15</td>
                            <td>B2MACTIVE</td>
                            <td>RW</td>
                            <td>Revision A: The B2M_STATE from the BLE Core transitioned into the active state  Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is deasserted (1 -> 0)<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>14</td>
                            <td>B2MSLEEP</td>
                            <td>RW</td>
                            <td>The B2M_STATE from the BLE Core transitioned into the sleep state<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>13</td>
                            <td>CQERR</td>
                            <td>RW</td>
                            <td>Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>12</td>
                            <td>CQUPD</td>
                            <td>RW</td>
                            <td>Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>11</td>
                            <td>CQPAUSED</td>
                            <td>RW</td>
                            <td>Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>10</td>
                            <td>DERR</td>
                            <td>RW</td>
                            <td>DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>9</td>
                            <td>DCMP</td>
                            <td>RW</td>
                            <td>DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>8</td>
                            <td>BLECSSTAT</td>
                            <td>RW</td>
                            <td>BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core.
Transfers to the BLE Core should only be done when this signal is high.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>7</td>
                            <td>BLECIRQ</td>
                            <td>RW</td>
                            <td>BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>6</td>
                            <td>ICMD</td>
                            <td>RW</td>
                            <td>illegal command interrupt. Asserted when a command is written when an active command is in progress.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>5</td>
                            <td>IACC</td>
                            <td>RW</td>
                            <td>illegal FIFO access interrupt. Asserted when there is a overflow or underflow event<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>4</td>
                            <td>B2MST</td>
                            <td>RW</td>
                            <td>B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>3</td>
                            <td>FOVFL</td>
                            <td>RW</td>
                            <td>Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>2</td>
                            <td>FUNDFL</td>
                            <td>RW</td>
                            <td>Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>THR</td>
                            <td>RW</td>
                            <td>FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field.
For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>CMDCMP</td>
                            <td>RW</td>
                            <td>Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="INTSTAT" class="panel-title">INTSTAT - IO Master Interrupts: Status</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C224</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Read bits from this register to discover the cause of a recent interrupt.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="15">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">B2MSHUTDN
                                <br>0x0</td>

                            <td align="center" colspan="1">B2MACTIVE
                                <br>0x0</td>

                            <td align="center" colspan="1">B2MSLEEP
                                <br>0x0</td>

                            <td align="center" colspan="1">CQERR
                                <br>0x0</td>

                            <td align="center" colspan="1">CQUPD
                                <br>0x0</td>

                            <td align="center" colspan="1">CQPAUSED
                                <br>0x0</td>

                            <td align="center" colspan="1">DERR
                                <br>0x0</td>

                            <td align="center" colspan="1">DCMP
                                <br>0x0</td>

                            <td align="center" colspan="1">BLECSSTAT
                                <br>0x0</td>

                            <td align="center" colspan="1">BLECIRQ
                                <br>0x0</td>

                            <td align="center" colspan="1">ICMD
                                <br>0x0</td>

                            <td align="center" colspan="1">IACC
                                <br>0x0</td>

                            <td align="center" colspan="1">B2MST
                                <br>0x0</td>

                            <td align="center" colspan="1">FOVFL
                                <br>0x0</td>

                            <td align="center" colspan="1">FUNDFL
                                <br>0x0</td>

                            <td align="center" colspan="1">THR
                                <br>0x0</td>

                            <td align="center" colspan="1">CMDCMP
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:17</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>16</td>
                            <td>B2MSHUTDN</td>
                            <td>RW</td>
                            <td>Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state  Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is deasserted (1 -> 0)<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>15</td>
                            <td>B2MACTIVE</td>
                            <td>RW</td>
                            <td>Revision A: The B2M_STATE from the BLE Core transitioned into the active state  Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is deasserted (1 -> 0)<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>14</td>
                            <td>B2MSLEEP</td>
                            <td>RW</td>
                            <td>The B2M_STATE from the BLE Core transitioned into the sleep state<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>13</td>
                            <td>CQERR</td>
                            <td>RW</td>
                            <td>Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>12</td>
                            <td>CQUPD</td>
                            <td>RW</td>
                            <td>Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>11</td>
                            <td>CQPAUSED</td>
                            <td>RW</td>
                            <td>Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>10</td>
                            <td>DERR</td>
                            <td>RW</td>
                            <td>DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>9</td>
                            <td>DCMP</td>
                            <td>RW</td>
                            <td>DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>8</td>
                            <td>BLECSSTAT</td>
                            <td>RW</td>
                            <td>BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core.
Transfers to the BLE Core should only be done when this signal is high.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>7</td>
                            <td>BLECIRQ</td>
                            <td>RW</td>
                            <td>BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>6</td>
                            <td>ICMD</td>
                            <td>RW</td>
                            <td>illegal command interrupt. Asserted when a command is written when an active command is in progress.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>5</td>
                            <td>IACC</td>
                            <td>RW</td>
                            <td>illegal FIFO access interrupt. Asserted when there is a overflow or underflow event<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>4</td>
                            <td>B2MST</td>
                            <td>RW</td>
                            <td>B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>3</td>
                            <td>FOVFL</td>
                            <td>RW</td>
                            <td>Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>2</td>
                            <td>FUNDFL</td>
                            <td>RW</td>
                            <td>Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>THR</td>
                            <td>RW</td>
                            <td>FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field.
For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>CMDCMP</td>
                            <td>RW</td>
                            <td>Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="INTCLR" class="panel-title">INTCLR - IO Master Interrupts: Clear</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C228</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Write a 1 to a bit in this register to clear the interrupt status associated with that bit.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="15">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">B2MSHUTDN
                                <br>0x0</td>

                            <td align="center" colspan="1">B2MACTIVE
                                <br>0x0</td>

                            <td align="center" colspan="1">B2MSLEEP
                                <br>0x0</td>

                            <td align="center" colspan="1">CQERR
                                <br>0x0</td>

                            <td align="center" colspan="1">CQUPD
                                <br>0x0</td>

                            <td align="center" colspan="1">CQPAUSED
                                <br>0x0</td>

                            <td align="center" colspan="1">DERR
                                <br>0x0</td>

                            <td align="center" colspan="1">DCMP
                                <br>0x0</td>

                            <td align="center" colspan="1">BLECSSTAT
                                <br>0x0</td>

                            <td align="center" colspan="1">BLECIRQ
                                <br>0x0</td>

                            <td align="center" colspan="1">ICMD
                                <br>0x0</td>

                            <td align="center" colspan="1">IACC
                                <br>0x0</td>

                            <td align="center" colspan="1">B2MST
                                <br>0x0</td>

                            <td align="center" colspan="1">FOVFL
                                <br>0x0</td>

                            <td align="center" colspan="1">FUNDFL
                                <br>0x0</td>

                            <td align="center" colspan="1">THR
                                <br>0x0</td>

                            <td align="center" colspan="1">CMDCMP
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:17</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>16</td>
                            <td>B2MSHUTDN</td>
                            <td>RW</td>
                            <td>Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state  Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is deasserted (1 -> 0)<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>15</td>
                            <td>B2MACTIVE</td>
                            <td>RW</td>
                            <td>Revision A: The B2M_STATE from the BLE Core transitioned into the active state  Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is deasserted (1 -> 0)<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>14</td>
                            <td>B2MSLEEP</td>
                            <td>RW</td>
                            <td>The B2M_STATE from the BLE Core transitioned into the sleep state<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>13</td>
                            <td>CQERR</td>
                            <td>RW</td>
                            <td>Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>12</td>
                            <td>CQUPD</td>
                            <td>RW</td>
                            <td>Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>11</td>
                            <td>CQPAUSED</td>
                            <td>RW</td>
                            <td>Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>10</td>
                            <td>DERR</td>
                            <td>RW</td>
                            <td>DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>9</td>
                            <td>DCMP</td>
                            <td>RW</td>
                            <td>DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>8</td>
                            <td>BLECSSTAT</td>
                            <td>RW</td>
                            <td>BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core.
Transfers to the BLE Core should only be done when this signal is high.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>7</td>
                            <td>BLECIRQ</td>
                            <td>RW</td>
                            <td>BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>6</td>
                            <td>ICMD</td>
                            <td>RW</td>
                            <td>illegal command interrupt. Asserted when a command is written when an active command is in progress.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>5</td>
                            <td>IACC</td>
                            <td>RW</td>
                            <td>illegal FIFO access interrupt. Asserted when there is a overflow or underflow event<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>4</td>
                            <td>B2MST</td>
                            <td>RW</td>
                            <td>B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>3</td>
                            <td>FOVFL</td>
                            <td>RW</td>
                            <td>Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>2</td>
                            <td>FUNDFL</td>
                            <td>RW</td>
                            <td>Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>THR</td>
                            <td>RW</td>
                            <td>FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field.
For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>CMDCMP</td>
                            <td>RW</td>
                            <td>Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="INTSET" class="panel-title">INTSET - IO Master Interrupts: Set</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C22C</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="15">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">B2MSHUTDN
                                <br>0x0</td>

                            <td align="center" colspan="1">B2MACTIVE
                                <br>0x0</td>

                            <td align="center" colspan="1">B2MSLEEP
                                <br>0x0</td>

                            <td align="center" colspan="1">CQERR
                                <br>0x0</td>

                            <td align="center" colspan="1">CQUPD
                                <br>0x0</td>

                            <td align="center" colspan="1">CQPAUSED
                                <br>0x0</td>

                            <td align="center" colspan="1">DERR
                                <br>0x0</td>

                            <td align="center" colspan="1">DCMP
                                <br>0x0</td>

                            <td align="center" colspan="1">BLECSSTAT
                                <br>0x0</td>

                            <td align="center" colspan="1">BLECIRQ
                                <br>0x0</td>

                            <td align="center" colspan="1">ICMD
                                <br>0x0</td>

                            <td align="center" colspan="1">IACC
                                <br>0x0</td>

                            <td align="center" colspan="1">B2MST
                                <br>0x0</td>

                            <td align="center" colspan="1">FOVFL
                                <br>0x0</td>

                            <td align="center" colspan="1">FUNDFL
                                <br>0x0</td>

                            <td align="center" colspan="1">THR
                                <br>0x0</td>

                            <td align="center" colspan="1">CMDCMP
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:17</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>16</td>
                            <td>B2MSHUTDN</td>
                            <td>RW</td>
                            <td>Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state  Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is deasserted (1 -> 0)<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>15</td>
                            <td>B2MACTIVE</td>
                            <td>RW</td>
                            <td>Revision A: The B2M_STATE from the BLE Core transitioned into the active state  Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is deasserted (1 -> 0)<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>14</td>
                            <td>B2MSLEEP</td>
                            <td>RW</td>
                            <td>The B2M_STATE from the BLE Core transitioned into the sleep state<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>13</td>
                            <td>CQERR</td>
                            <td>RW</td>
                            <td>Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>12</td>
                            <td>CQUPD</td>
                            <td>RW</td>
                            <td>Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>11</td>
                            <td>CQPAUSED</td>
                            <td>RW</td>
                            <td>Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>10</td>
                            <td>DERR</td>
                            <td>RW</td>
                            <td>DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>9</td>
                            <td>DCMP</td>
                            <td>RW</td>
                            <td>DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>8</td>
                            <td>BLECSSTAT</td>
                            <td>RW</td>
                            <td>BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core.
Transfers to the BLE Core should only be done when this signal is high.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>7</td>
                            <td>BLECIRQ</td>
                            <td>RW</td>
                            <td>BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>6</td>
                            <td>ICMD</td>
                            <td>RW</td>
                            <td>illegal command interrupt. Asserted when a command is written when an active command is in progress.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>5</td>
                            <td>IACC</td>
                            <td>RW</td>
                            <td>illegal FIFO access interrupt. Asserted when there is a overflow or underflow event<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>4</td>
                            <td>B2MST</td>
                            <td>RW</td>
                            <td>B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>3</td>
                            <td>FOVFL</td>
                            <td>RW</td>
                            <td>Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>2</td>
                            <td>FUNDFL</td>
                            <td>RW</td>
                            <td>Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>THR</td>
                            <td>RW</td>
                            <td>FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field.
For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>CMDCMP</td>
                            <td>RW</td>
                            <td>Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="DMATRIGEN" class="panel-title">DMATRIGEN - DMA Trigger Enable Register</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C230</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be
transferred via the DMA operation, and can be used to adjust the latency of data to/from the IOM module to/from the DMA target. DMA transfers are broken into smaller transfers internally of up to
16 bytes each, and multiple trigger events can be used to complete the entire programmed DMA transfer.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="30">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">DTHREN
                                <br>0x0</td>

                            <td align="center" colspan="1">DCMDCMPEN
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:2</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>DTHREN</td>
                            <td>RW</td>
                            <td>Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes), the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO, and will transfer (WTHR/4) number of words
or, if the number of words left to transfer is less than the WTHR value, will transfer the remaining byte count.
For P2M DMA operations, the trigger will assert when the read FIFO has (RTHR/4) words available in the read FIFO, and will transfer (RTHR/4) words to SRAM. This trigger will NOT assert when the transaction
completes and there are less than RTHR bytes left in the FIFO, since the RTHR has not been reached. In this case, enabling the CMDCMP trigger will transfer the remaining data from the command. If the CMDCMP trigger is not enabled, the module will initiate a transfer when the amount of data in the FIFO is equal to or greater than the remaining data in the DMA. In cases where one DMA setup covers multiple commands, this will only occur at the end of the last transaction when the DMA is near complete.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>DCMDCMPEN</td>
                            <td>RW</td>
                            <td>Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered, the number of words transferred will be the lesser of the remaining TOTCOUNT bytes, or the number of bytes in the FIFO when the command completed. If this is disabled, and the number of bytes in the FIFO is equal or greater than the TOTCOUNT bytes, a transfer of TOTCOUNT bytes will be done to ensure read data is stored when the DMA is completed.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="DMATRIGSTAT" class="panel-title">DMATRIGSTAT - DMA Trigger Status Register</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C234</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="29">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">DTOTCMP
                                <br>0x0</td>

                            <td align="center" colspan="1">DTHR
                                <br>0x0</td>

                            <td align="center" colspan="1">DCMDCMP
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:3</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>2</td>
                            <td>DTOTCMP</td>
                            <td>RO</td>
                            <td>DMA triggered when DCMDCMP = 0, and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is
disabled and there is enough data in the FIFO to complete the DMA operation.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>DTHR</td>
                            <td>RO</td>
                            <td>Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>DCMDCMP</td>
                            <td>RO</td>
                            <td>Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="DMACFG" class="panel-title">DMACFG - DMA Configuration Register</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C238</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Configuration control of the DMA process, including the direction of DMA, and enablement of DMA</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="22">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">DPWROFF
                                <br>0x0</td>

                            <td align="center" colspan="1">DMAPRI
                                <br>0x0</td>

                            <td align="center" colspan="6">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">DMADIR
                                <br>0x0</td>

                            <td align="center" colspan="1">DMAEN
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:10</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>9</td>
                            <td>DPWROFF</td>
                            <td>RW</td>
                            <td>Power off module after DMA is complete. If this bit is active, the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain, power down will not be performed.<br><br>
                                 DIS                  = 0x0 - Power off disabled<br>
                             EN                   = 0x1 - Power off enabled</td>
                        </tr>

                        <tr>
                            <td>8</td>
                            <td>DMAPRI</td>
                            <td>RW</td>
                            <td>Sets the Priority of the DMA request<br><br>
                                 LOW                  = 0x0 - Low Priority (service as best effort)<br>
                             HIGH                 = 0x1 - High Priority (service immediately)</td>
                        </tr>

                        <tr>
                            <td>7:2</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>DMADIR</td>
                            <td>RW</td>
                            <td>Direction<br><br>
                                 P2M                  = 0x0 - Peripheral to Memory (SRAM) transaction. To be set when doing IOM read operations, i.e., reading data from external devices.<br>
                             M2P                  = 0x1 - Memory to Peripheral transaction. To be set when doing IOM write operations, i.e., writing data to external devices.</td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>DMAEN</td>
                            <td>RW</td>
                            <td>DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command<br><br>
                                 DIS                  = 0x0 - Disable DMA Function<br>
                             EN                   = 0x1 - Enable DMA Function</td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="DMATOTCOUNT" class="panel-title">DMATOTCOUNT - DMA Total Transfer Count</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C23C</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred, and will be 0 at the completion of the DMA operation.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="20">RSRVDD
                                <br>0x0</td>

                            <td align="center" colspan="12">TOTCOUNT
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:12</td>
                            <td>RSRVDD</td>
                            <td>RO</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>11:0</td>
                            <td>TOTCOUNT</td>
                            <td>RW</td>
                            <td>Triggered DMA from Command complete event occurred. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="DMATARGADDR" class="panel-title">DMATARGADDR - DMA Target Address Register</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C240</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>The source or destination address internal the SRAM for the DMA data. For write operations, this can only be SRAM data (ADDR bit 28 = 1); For read operations, this can be either SRAM or FLASH (ADDR bit 28 = 0)</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="3">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">TARGADDR28
                                <br>0x0</td>

                            <td align="center" colspan="8">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="20">TARGADDR
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:29</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>28</td>
                            <td>TARGADDR28</td>
                            <td>RW</td>
                            <td>Bit 28 of the target byte address for source of DMA (either read or write). In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written.
Setting to '1' will select the SRAM. Setting to '0' will select the flash<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>27:20</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>19:0</td>
                            <td>TARGADDR</td>
                            <td>RW</td>
                            <td>Bits [19:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment, and does not have to be word aligned. In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="DMASTAT" class="panel-title">DMASTAT - DMA Status Register</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C244</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Status of the DMA operation currently in progress.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="29">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">DMAERR
                                <br>0x0</td>

                            <td align="center" colspan="1">DMACPL
                                <br>0x0</td>

                            <td align="center" colspan="1">DMATIP
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:3</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>2</td>
                            <td>DMAERR</td>
                            <td>RW</td>
                            <td>DMA Error. This active high bit signals that an error was encountered during the DMA operation.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>DMACPL</td>
                            <td>RW</td>
                            <td>DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>DMATIP</td>
                            <td>RO</td>
                            <td>DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data, transferring data, or waiting for priority.
All of these will be indicated with a 1. A 0 will indicate that the DMA is fully complete and no further transactions will be done. This bit is read only.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="CQCFG" class="panel-title">CQCFG - Command Queue Configuration Register</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C248</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Controls parameters and options for execution of the command queue operation. To enable command queue, create this in memory, set the address, and enable it with a write to CQEN</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="30">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">CQPRI
                                <br>0x0</td>

                            <td align="center" colspan="1">CQEN
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:2</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>CQPRI</td>
                            <td>RW</td>
                            <td>Sets the Priority of the command queue DMA request.<br><br>
                                 LOW                  = 0x0 - Low Priority (service as best effort)<br>
                             HIGH                 = 0x1 - High Priority (service immediately)</td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>CQEN</td>
                            <td>RW</td>
                            <td>Command queue enable. When set, will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled
using a CQ executed write to this bit as well.<br><br>
                                 DIS                  = 0x0 - Disable CQ Function<br>
                             EN                   = 0x1 - Enable CQ Function</td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="CQADDR" class="panel-title">CQADDR - CQ Target Read Address Register</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C24C</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses, and is the live version of the register. The register can also be
written by the Command Queue operation itself, allowing the relocation of successive CQ fetches. In this case, the new CQ address will be used for the next CQ address/data fetch</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="3">RSRVD2
                                <br>0x0</td>

                            <td align="center" colspan="1">CQADDR28
                                <br>0x0</td>

                            <td align="center" colspan="8">RSRVD1
                                <br>0x0</td>

                            <td align="center" colspan="18">CQADDR
                                <br>0x0</td>

                            <td align="center" colspan="2">RSRVD0
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:29</td>
                            <td>RSRVD2</td>
                            <td>RO</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>28</td>
                            <td>CQADDR28</td>
                            <td>RW</td>
                            <td>Bit 28 of target byte address for source of CQ (read only). Used to denote Flash (0) or SRAM (1) access<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>27:20</td>
                            <td>RSRVD1</td>
                            <td>RO</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>19:2</td>
                            <td>CQADDR</td>
                            <td>RW</td>
                            <td>Bits 19:2 of target byte address for source of CQ (read only). The buffer must be aligned on a word boundary<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>1:0</td>
                            <td>RSRVD0</td>
                            <td>RO</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="CQSTAT" class="panel-title">CQSTAT - Command Queue Status Register</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C250</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Provides the status of the command queue operation. If the command queue is disabled, these bits will be cleared. The bits are read only</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="29">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">CQERR
                                <br>0x0</td>

                            <td align="center" colspan="1">CQPAUSED
                                <br>0x0</td>

                            <td align="center" colspan="1">CQTIP
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:3</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>2</td>
                            <td>CQERR</td>
                            <td>RW</td>
                            <td>Command queue processing error. This active high bit signals that an error was encountered during the CQ  operation.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>CQPAUSED</td>
                            <td>RO</td>
                            <td>Command queue operation is currently paused.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>CQTIP</td>
                            <td>RO</td>
                            <td>Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="CQFLAGS" class="panel-title">CQFLAGS - Command Queue Flag Register</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C254</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Provides the current status of the SWFLAGS (bits 7:0) and the hardware generated flags (15:8). A '1' will pause the CQ operation if it the same bit is enabled in the CQPAUSEEN register</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="16">CQIRQMASK
                                <br>0x0</td>

                            <td align="center" colspan="16">CQFLAGS
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:16</td>
                            <td>CQIRQMASK</td>
                            <td>RW</td>
                            <td>Provides for a per-bit mask of the flags used to invoke an interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt, if the CQWT_int interrupt is enabled.
Bits definitions are the same as CQPAUSE<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>15:0</td>
                            <td>CQFLAGS</td>
                            <td>RO</td>
                            <td>Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="CQSETCLEAR" class="panel-title">CQSETCLEAR - Command Queue Flag Set/Clear Register</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C258</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields, allowing for setting, clearing or toggling the value in the software flags. Priority when the same bit
is enabled in each field is toggle, then set, then clear.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="8">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="8">CQFCLR
                                <br>0x0</td>

                            <td align="center" colspan="8">CQFTGL
                                <br>0x0</td>

                            <td align="center" colspan="8">CQFSET
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:24</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>23:16</td>
                            <td>CQFCLR</td>
                            <td>WO</td>
                            <td>Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>15:8</td>
                            <td>CQFTGL</td>
                            <td>WO</td>
                            <td>Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>7:0</td>
                            <td>CQFSET</td>
                            <td>WO</td>
                            <td>Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="CQPAUSEEN" class="panel-title">CQPAUSEEN - Command Queue Pause Enable Register</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C25C</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1', CQ processing will halt until either value is changed to '0'.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="16">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="16">CQPEN
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:16</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>15:0</td>
                            <td>CQPEN</td>
                            <td>RW</td>
                            <td>Enables the specified event to pause command processing when active<br><br>
                                 CNTEQ                = 0x8000 - Pauses command queue processing when HWCNT matches SWCNT<br>
                             BLEXOREN             = 0x4000 - Pause command queue when input BLE bit XORed with SWFLAG4 is '1'<br>
                             IOMXOREN             = 0x2000 - Pause command queue when input IOM bit XORed with SWFLAG3 is '1'<br>
                             GPIOXOREN            = 0x1000 - Pause command queue when input GPIO irq_bit XORed with SWFLAG2 is '1'<br>
                             MSPI1XNOREN          = 0x800 - Pause command queue when input MSPI1 bit XNORed with SWFLAG1 is '1'<br>
                             MSPI0XNOREN          = 0x400 - Pause command queue when input MSPI0 bit XNORed with SWFLAG0 is '1'<br>
                             MSPI1XOREN           = 0x200 - Pause command queue when input MSPI1 bit XORed with SWFLAG1 is '1'<br>
                             MSPI0XOREN           = 0x100 - Pause command queue when input MSPI0 bit XORed with SWFLAG0 is '1'<br>
                             SWFLAGEN7            = 0x80 - Pause the command queue when software flag bit 7 is '1'.<br>
                             SWFLAGEN6            = 0x40 - Pause the command queue when software flag bit 7 is '1'<br>
                             SWFLAGEN5            = 0x20 - Pause the command queue when software flag bit 7 is '1'<br>
                             SWFLAGEN4            = 0x10 - Pause the command queue when software flag bit 7 is '1'<br>
                             SWFLAGEN3            = 0x8 - Pause the command queue when software flag bit 7 is '1'<br>
                             SWFLAGEN2            = 0x4 - Pause the command queue when software flag bit 7 is '1'<br>
                             SWFLAGEN1            = 0x2 - Pause the command queue when software flag bit 7 is '1'<br>
                             SWFLGEN0             = 0x1 - Pause the command queue when software flag bit 7 is '1'</td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="CQCURIDX" class="panel-title">CQCURIDX - IOM Command Queue current index value. Compared to the CQENDIDX reg contents to generate the IDXEQ Pause event for command queue</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C260</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Current index value, targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and
this current index equals the CQENDIDX register value. This will only pause when the values are equal.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="24">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="8">CQCURIDX
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:8</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>7:0</td>
                            <td>CQCURIDX</td>
                            <td>RW</td>
                            <td>Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="CQENDIDX" class="panel-title">CQENDIDX - IOM Command Queue current index value. Compared to the CQCURIDX reg contents to generate the IDXEQ Pause event for command queue</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C264</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>End index value, targeted to be written by software to indicate the last valid register pair contained within the command queue for register write operations within the command queue.
This is compared to the CQCURIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and
this current index equals the CQCURIDX register value. This will only pause when the values are equal.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="24">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="8">CQENDIDX
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:8</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>7:0</td>
                            <td>CQENDIDX</td>
                            <td>RW</td>
                            <td>Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="STATUS" class="panel-title">STATUS - IOM Module Status Register</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C268</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>General status of the IOM module command execution.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="29">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">IDLEST
                                <br>0x0</td>

                            <td align="center" colspan="1">CMDACT
                                <br>0x0</td>

                            <td align="center" colspan="1">ERR
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:3</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>2</td>
                            <td>IDLEST</td>
                            <td>RO</td>
                            <td>indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to hold-offs from data availability, or as the command gets propagated into the logic from the registers.<br><br>
                                 IDLE                 = 0x1 - The I/O state machine is in the idle state.</td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>CMDACT</td>
                            <td>RO</td>
                            <td>Indicates if the active I/O Command is currently processing a transaction, or command is complete, but the FIFO pointers are still synchronizing internally. This bit will go high at
the start of the transaction, and will go low when the command is complete, and the data and pointers within the FIFO have been synchronized.<br><br>
                                 ACTIVE               = 0x1 - An I/O command is active. Indicates the active module has an active command and is processing this. Deasserted when the command is completed.</td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>ERR</td>
                            <td>RO</td>
                            <td>Bit has been deprecated. Please refer to the other error indicators. This will always return 0.<br><br>
                                 ERROR                = 0x1 - Bit has been deprecated and will always return 0.</td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="MSPICFG" class="panel-title">MSPICFG - SPI module master configuration</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C300</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Controls the configuration of the SPI master module, including POL/PHA, LSB, flow control, and delays for MISO and MOSI</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="1">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">MSPIRST
                                <br>0x1</td>

                            <td align="center" colspan="3">DOUTDLY
                                <br>0x0</td>

                            <td align="center" colspan="3">DINDLY
                                <br>0x0</td>

                            <td align="center" colspan="1">SPILSB
                                <br>0x0</td>

                            <td align="center" colspan="1">RDFCPOL
                                <br>0x0</td>

                            <td align="center" colspan="1">WTFCPOL
                                <br>0x0</td>

                            <td align="center" colspan="3">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">RDFC
                                <br>0x0</td>

                            <td align="center" colspan="1">WTFC
                                <br>0x0</td>

                            <td align="center" colspan="13">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">FULLDUP
                                <br>0x0</td>

                            <td align="center" colspan="1">SPHA
                                <br>0x0</td>

                            <td align="center" colspan="1">SPOL
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>30</td>
                            <td>MSPIRST</td>
                            <td>RW</td>
                            <td>Bit is deprecated. setting it will have no effect.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>29:27</td>
                            <td>DOUTDLY</td>
                            <td>RW</td>
                            <td>Delay tap to use for the output signal (MOSI). This give more hold time on the output data.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>26:24</td>
                            <td>DINDLY</td>
                            <td>RW</td>
                            <td>Delay tap to use for the input signal (MISO). This gives more hold time on the input data.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>23</td>
                            <td>SPILSB</td>
                            <td>RW</td>
                            <td>Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first.<br><br>
                                 MSB                  = 0x0 - Send and receive MSB bit first<br>
                             LSB                  = 0x1 - Send and receive LSB bit first</td>
                        </tr>

                        <tr>
                            <td>22</td>
                            <td>RDFCPOL</td>
                            <td>RW</td>
                            <td>Selects the read flow control signal polarity. When set, the clock will be held low until the flow control is deasserted.<br><br>
                                 NORMAL               = 0x0 - SPI_STATUS signal from BLE Core high(1) creates flow control and new read SPI transactions will not be started until the signal goes low.(default)<br>
                             INVERTED             = 0x1 - SPI_STATUS signal from BLE Core low(0) creates flow control and new read SPI transactions will not be started until the signal goes high.</td>
                        </tr>

                        <tr>
                            <td>21</td>
                            <td>WTFCPOL</td>
                            <td>RW</td>
                            <td>Selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of this bit. (For example: WTFCPOL = 0 will allow a SPI_STATUS=1 to pause transfers).<br><br>
                                 NORMAL               = 0x0 - SPI_STATUS signal from BLE Core high(1) creates flow control and new write SPI transactions will not be started until the signal goes low.(default)<br>
                             INVERTED             = 0x1 - SPI_STATUS signal from BLE Core high(1) creates low(0) control and new write SPI transactions will not be started until the signal goes high.</td>
                        </tr>

                        <tr>
                            <td>20:18</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>17</td>
                            <td>RDFC</td>
                            <td>RW</td>
                            <td>Enables flow control of new read transactions based on the SPI_STATUS signal from the BLE Core.<br><br>
                                 DIS                  = 0x0 - Read mode flow control disabled.<br>
                             EN                   = 0x1 - Read mode flow control enabled.</td>
                        </tr>

                        <tr>
                            <td>16</td>
                            <td>WTFC</td>
                            <td>RW</td>
                            <td>Enables flow control of new write transactions based on the SPI_STATUS signal from the BLE Core.<br><br>
                                 DIS                  = 0x0 - Write mode flow control disabled.<br>
                             EN                   = 0x1 - Write mode flow control enabled.</td>
                        </tr>

                        <tr>
                            <td>15:3</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>2</td>
                            <td>FULLDUP</td>
                            <td>RW</td>
                            <td>Full Duplex mode. Capture read data during writes operations<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>SPHA</td>
                            <td>RW</td>
                            <td>Selects the SPI phase; When 1, will shift the sampling edge by 1/2 clock.<br><br>
                                 SAMPLE_LEADING_EDGE  = 0x0 - Sample on the leading (first) clock edge, rising or falling dependent on the value of SPOL<br>
                             SAMPLE_TRAILING_EDGE = 0x1 - Sample on the trailing (second) clock edge, rising of falling dependent on the value of SPOL</td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>SPOL</td>
                            <td>RW</td>
                            <td>This bit selects SPI polarity.<br><br>
                                 CLK_BASE_0           = 0x0 - The initial value of the clock is 0.<br>
                             CLK_BASE_1           = 0x1 - The initial value of the clock is 1.</td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="BLECFG" class="panel-title">BLECFG - BLE Core Control</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C304</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Provides control of isolation and IO signals between the interface module and the BLE Core.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="16">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="2">SPIISOCTL
                                <br>0x0</td>

                            <td align="center" colspan="2">PWRISOCTL
                                <br>0x0</td>

                            <td align="center" colspan="1">STAYASLEEP
                                <br>0x0</td>

                            <td align="center" colspan="1">FRCCLK
                                <br>0x0</td>

                            <td align="center" colspan="1">MCUFRCSLP
                                <br>0x0</td>

                            <td align="center" colspan="1">WT4ACTOFF
                                <br>0x0</td>

                            <td align="center" colspan="2">BLEHREQCTL
                                <br>0x0</td>

                            <td align="center" colspan="2">DCDCFLGCTL
                                <br>0x0</td>

                            <td align="center" colspan="2">WAKEUPCTL
                                <br>0x0</td>

                            <td align="center" colspan="1">BLERSTN
                                <br>0x0</td>

                            <td align="center" colspan="1">PWRSMEN
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:16</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>15:14</td>
                            <td>SPIISOCTL</td>
                            <td>RW</td>
                            <td>Configuration of BLEH isolation controls for SPI related signals.<br><br>
                                 ON                   = 0x3 - SPI signals from BLE Core to/from MCU Core are isolated.<br>
                             OFF                  = 0x2 - SPI signals from BLE Core to/from MCU Core are not isolated.<br>
                             AUTO                 = 0x0 - SPI signals from BLE Core to/from MCU Core are automatically isolated by the logic</td>
                        </tr>

                        <tr>
                            <td>13:12</td>
                            <td>PWRISOCTL</td>
                            <td>RW</td>
                            <td>Configuration of BLEH isolation control for power related signals.<br><br>
                                 ON                   = 0x3 - BLEH power signal isolation to on (isolated).<br>
                             OFF                  = 0x2 - BLEH power signal isolation to off (not isolated).<br>
                             AUTO                 = 0x0 - BLEH Power signal isolation is controlled automatically through the interface logic</td>
                        </tr>

                        <tr>
                            <td>11</td>
                            <td>STAYASLEEP</td>
                            <td>RW</td>
                            <td>Set to prevent the BLE power control module from waking up the BLE Core after going into power down. To be used for graceful shutdown, set by software prior to powering off and will allow assertion of reset from sleep state.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>10</td>
                            <td>FRCCLK</td>
                            <td>RW</td>
                            <td>Force the clock in the BLEIF to be always running<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>9</td>
                            <td>MCUFRCSLP</td>
                            <td>RW</td>
                            <td>Force power state machine to go to the sleep state. Intended for debug only. Has no effect on the actual BLE Core state, only the state of the BLEIF interface state machine.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>8</td>
                            <td>WT4ACTOFF</td>
                            <td>RW</td>
                            <td>Debug control of BLEIF power state machine. Allows transition into the active state in the BLEIF state without waiting for DCDC request from BLE Core.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>7:6</td>
                            <td>BLEHREQCTL</td>
                            <td>RW</td>
                            <td>BLEH power on request override. The value of this field will be sent to the BLE Core when the PWRSM is off. Otherwise, the value is supplied from internal logic.<br><br>
                                 ON                   = 0x3 - BLEH Power-on reg signal is set to on (1).<br>
                             OFF                  = 0x2 - BLEH Power-on signal is set to off (0).<br>
                             AUTO                 = 0x0 - BLEH Power-on signal is controlled by the PWRSM logic and automatically controlled</td>
                        </tr>

                        <tr>
                            <td>5:4</td>
                            <td>DCDCFLGCTL</td>
                            <td>RW</td>
                            <td>DCDCFLG signal override. The value of this field will be sent to the BLE Core when the PWRSM is off. Otherwise, the value is supplied from internal logic.<br><br>
                                 ON                   = 0x3 - DCDC Flag signal is set to on (1).<br>
                             OFF                  = 0x2 - DCDC Flag signal is set to off (0).<br>
                             AUTO                 = 0x0 - DCDC Flag signal is controlled by the PWRSM logic and automatically controlled</td>
                        </tr>

                        <tr>
                            <td>3:2</td>
                            <td>WAKEUPCTL</td>
                            <td>RW</td>
                            <td>WAKE signal override. Controls the source of the WAKE signal to the BLE Core.<br><br>
                                 ON                   = 0x3 - Wake signal is set to on (1).<br>
                             OFF                  = 0x2 - Wake signal is set to off (0).<br>
                             AUTO                 = 0x0 - Wake signal is controlled by the PWRSM logic and automatically controlled</td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>BLERSTN</td>
                            <td>RW</td>
                            <td>Reset line to the BLE Core. This will reset the BLE core when asserted ('0') and must be written to '1' prior to performing any BTLE related operations to the core.<br><br>
                                 ACTIVE               = 0x1 - The reset signal is active (0)<br>
                             INACTIVE             = 0x0 - The reset signal is inactive (1)</td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>PWRSMEN</td>
                            <td>RW</td>
                            <td>Enable the power state machine for automatic sequencing and control of power states of the BLE Core module.<br><br>
                                 ON                   = 0x1 - Internal power state machine is enabled and will sequence the BLEH power domain as indicated in the design document. Overrides for the power signals are not enabled.<br>
                             OFF                  = 0x0 - Internal power state machine is disabled and will not sequence the BLEH power domain. The values of the overrides will be used to drive the output sequencing signals</td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="PWRCMD" class="panel-title">PWRCMD - BLE Power command interface</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C308</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Sends power related commands to the power state machine in the BLE IF module.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="30">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">RESTART
                                <br>0x0</td>

                            <td align="center" colspan="1">WAKEREQ
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:2</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>RESTART</td>
                            <td>WO</td>
                            <td>Restart the BLE Core after going into the shutdown state. Only valid when in the shutdown state.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>WAKEREQ</td>
                            <td>WO</td>
                            <td>Wake request from the MCU. When asserted (1), the BLE Interface logic will assert the wakeup request signal to the BLE Core. Only recognized when in the sleep state<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="BSTATUS" class="panel-title">BSTATUS - BLE Core status</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C30C</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Status of the BLE Core interface signals</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="19">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">BLEHREQ
                                <br>0x0</td>

                            <td align="center" colspan="1">BLEHACK
                                <br>0x0</td>

                            <td align="center" colspan="3">PWRST
                                <br>0x0</td>

                            <td align="center" colspan="1">BLEIRQ
                                <br>0x0</td>

                            <td align="center" colspan="1">WAKEUP
                                <br>0x0</td>

                            <td align="center" colspan="1">DCDCFLAG
                                <br>0x0</td>

                            <td align="center" colspan="1">DCDCREQ
                                <br>0x0</td>

                            <td align="center" colspan="1">SPISTATUS
                                <br>0x0</td>

                            <td align="center" colspan="3">B2MSTATE
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:13</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>12</td>
                            <td>BLEHREQ</td>
                            <td>RO</td>
                            <td>Value of the BLEHREQ signal to the power control unit. The BLEHREQ signal is sent from the BLEIF module to the power control module to request the BLEH power up. When the BLEHACK signal is asserted,
BLEH power is stable and ready for use.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>11</td>
                            <td>BLEHACK</td>
                            <td>RO</td>
                            <td>Value of the BLEHACK signal from the power control unit. If the signal is '1', the BLEH power is active and ready for use.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>10:8</td>
                            <td>PWRST</td>
                            <td>RO</td>
                            <td>Current status of the power state machine<br><br>
                                 OFF                  = 0x0 - Internal power state machine is disabled and will not sequence the BLEH power domain. The values of the overrides will be used to drive the output sequencing signals<br>
                             INIT                 = 0x1 - Initialization state. BLEH not powered<br>
                             PWRON                = 0x2 - Waiting for the power-up of the BLEH<br>
                             ACTIVE               = 0x3 - The BLE Core is powered and active<br>
                             SLEEP                = 0x6 - The BLE Core has entered sleep mode and the power request is inactive<br>
                             SHUTDOWN             = 0x4 - The BLE Core is in shutdown mode</td>
                        </tr>

                        <tr>
                            <td>7</td>
                            <td>BLEIRQ</td>
                            <td>RO</td>
                            <td>Status of the BLEIRQ signal from the BLE Core. A value of 1 indicates that read data is available in the core and a read operation needs to be performed.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>6</td>
                            <td>WAKEUP</td>
                            <td>RO</td>
                            <td>Value of the WAKEUP signal to the BLE Core . The WAKEUP signals is sent from the BLEIF to the BLECORE to request the BLE Core transition from sleep state to active state.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>5</td>
                            <td>DCDCFLAG</td>
                            <td>RO</td>
                            <td>Value of the DCDCFLAG signal to the BLE Core. The DCDCFLAG is a signal to the BLE Core indicating that the BLEH power is active.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>4</td>
                            <td>DCDCREQ</td>
                            <td>RO</td>
                            <td>Value of the DCDCREQ signal from the BLE Core. The DCDCREQ signal is sent from the core to the BLEIF module when the BLE core requires BLEH power to be active. When activated, this is
indicated by DCDCFLAG going to 1.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>3</td>
                            <td>SPISTATUS</td>
                            <td>RO</td>
                            <td>Value of the SPISTATUS signal from the BLE Core. The signal is asserted when the BLE Core is able to accept write data via the SPI interface. Data should be transmitted to the
BLE core only when this signal is 1. The hardware will automatically wait for this signal prior to performing a write operation if flow control is active.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>2:0</td>
                            <td>B2MSTATE</td>
                            <td>RO</td>
                            <td>State of the BLE Core logic.<br><br>
                                 RESET                = 0x0 - Reset State<br>
                             Shutdown             = 0x0 - Shutdown state<br>
                             Sleep                = 0x1 - Sleep state.<br>
                             Standby              = 0x2 - Standby State<br>
                             Idle                 = 0x3 - Idle state<br>
                             Active               = 0x4 - Active state.</td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="BLEDBG" class="panel-title">BLEDBG - BLEIF Master Debug Register</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x5000C410</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Debug control</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="29">DBGDATA
                                <br>0x0</td>

                            <td align="center" colspan="1">APBCLKON
                                <br>0x0</td>

                            <td align="center" colspan="1">IOCLKON
                                <br>0x0</td>

                            <td align="center" colspan="1">DBGEN
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:3</td>
                            <td>DBGDATA</td>
                            <td>RW</td>
                            <td>Debug data<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>2</td>
                            <td>APBCLKON</td>
                            <td>RW</td>
                            <td>APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>IOCLKON</td>
                            <td>RW</td>
                            <td>IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>DBGEN</td>
                            <td>RW</td>
                            <td>Debug Enable. Setting this bit will enable the update of data within this register, otherwise it is clock gated for power savings<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

    </body>

    <hr size="1">
    <body>
        <div id="footer" align="right">
            <small>
                AmbiqSuite Register Documentation&nbsp;
                <a href="http://www.ambiqmicro.com">
                <img class="footer" src="../resources/ambiqmicro_logo.png" alt="Ambiq Micro"/></a>&nbsp&nbsp Copyright &copy; 2024&nbsp&nbsp<br />
                This documentation is licensed and distributed under the <a rel="license" href="http://opensource.org/licenses/BSD-3-Clause">BSD 3-Clause License</a>.&nbsp&nbsp<br/>
            </small>
        </div>
    </body>
</html>

